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HT95C200/20p/300/30p 8-bit cid type phone controller mcu rev. 0.10 1 october 1, 2002 features provide mask type and otp type version operating voltage range: fsk: 3.0v~5.5v others: 2.4v~5.5v program rom: 8k 16 bits data ram: ht95c300/30p: 2112 8 bits HT95C200/20p: 1152 8 bits up to 28 bidirectional i/o lines 16-bit table read instructions eight-level subroutine nesting timer: two 16-bit programmable timer/event counter real time clock (rtc) watchdog timer (wdt) programmable frequency divider (pfd) dual system clock: 32768hz, 3.58mhz four operating modes: idle mode, sleep mode, green mode and normal mode up to 1.117 s instruction cycle with 3.58mhz system clock built-in 3.58mhz dtmf generator built-in fsk decoder: supports bell 202 and v.23 supports ring and line reversal detection lcd driver: ht95c300/30p: 48 seg. 16 com. HT95C200/20p: 24 seg. 16 com. support 16 or 8 common driver pins ht95c300/30p: 12 segments can per nibble op - tion to bidirectional i/o lines HT95C200/20p: 8 commons can per byte option to bidirectional i/o lines lcd contrast can be adjusted by software or exter - nal resistor support two lcd frame frequency 64hz, 128hz built-in low battery detector all instructions in one or two machine cycles built-in dialer i/o 128-pin qfp package applications deluxe feature phone caller id phone cordless phone fax and answering machines other communication system preliminary general description the HT95C200/20p/300/30p are 8-bit high perfor - mance risc-like microcontrollers with built-in dtmf generator, fsk decoder and dialer i/o which provide mcu dialer implementation or system control features for telecom product application. the phone controller has a built-in program rom, data ram, lcd driver and a maximum of 28 i/o lines for high end products design. in addition, for power management purpose, it has a built-in frequency up conversion circuit (32768hz to 3.58mhz) which provides dual system clock and four types of operation modes. for example it can operate with low speed system clock rate of 32768hz in green mode with little power consumption. it can also operate with high speed system clock rate of 3.58mhz in normal mode for high performance operation. to ensure smooth dialer function and to avoid mcu shut-down in extreme low voltage situation, the dialer i/o circuit is built-in to generate hardware dialer signals such as on-hook, hold-line and hand-free. built-in real time clock and programmable frequency divider are provided for additional fancy features in product developments. the device is best suitable for feature phone products that comply with versatile dialer specification require - ments of different areas or countries.
selection table part no. operating voltage program memory data memory normal i/o dialer i/o lcd timer stack external interrupt dtmf generator fsk receiver package ht95a200 ht95a20p 2.4v~5.5v 4k 16 1152 8 28 8 16-bit 2 84 48ssop ht95a300 ht95a30p 2.4v~5.5v 8k 16 2112 8 28 8 16-bit 2 84 48ssop ht95l100 ht95l10p 2.4v~5.5v 4k 16 1152 8 16~20 8 16 8~20 8 16-bit 2 84 64qfp ht95l200 ht95l20p 2.4v~5.5v 8k 16 1152 8 20~28 8 24 8~24 16 16-bit 2 84 100qfp ht95l300 ht95l30p 2.4v~5.5v 8k 16 2112 8 16~28 8 36 16~48 16 16-bit 2 84 100qfp HT95C200 ht95c20p 2.4v~5.5v 8k 16 1152 8 20~28 8 24 8~24 16 16-bit 2 84 128qfp ht95c300 ht95c30p 2.4v~5.5v 8k 16 2112 8 16~28 8 36 16~48 16 16-bit 2 84 128qfp note: part numbers suffixed with p are otp devices, all others are mask version devices. block diagram HT95C200/20p/300/30p rev. 0.10 2 october 1, 2002 preliminary

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pin description pin name i/o description cpu vdd positive power supply vdd2 positive power supply for fsk decoder vss negative power supply, ground vss2 negative power supply for fsk decoder, ground x1 i a 32768hz crystal (or resonator) should be connected to this pin and x2. x2 o a 32768hz crystal (or resonator) should be connected to this pin and x1. xc i external low pass filter used for frequency up conversion circuit. res i schmitt trigger reset input, active low. int /tmr1 i schmitt trigger input for external interrupt or timer/event counter 1. no internal pull-high resistor. for int : edge trigger activated on a falling edge. for tmr1: activated on falling or rising transition edge, selected by software. tmr0 i schmitt trigger input for timer/event counter 0. no internal pull-high resistor. activated on falling or rising transition edge, selected by software. HT95C200/20p/300/30p rev. 0.10 4 october 1, 2002 preliminary 0 . 0 2

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pin name i/o description lcd driver seg0~seg23 o lcd panel segment outputs. seg24~seg35 o lcd panel segment outputs. (ht95c300/30p only) seg36~seg47 (pd0~pd7, pe0~pe3) o or i/o lcd panel segment outputs. (ht95c300/30p only) seg36~seg39, seg40~seg43 and seg44~seg47 can be nibble optioned to pd0~pd3, pd4~pd7 and pe0~pe3 by software. com0~com7 (pd0~pd7) o or i/o lcd panel common outputs. ht95c300/30p: can be optioned to com0~com7 or unused. HT95C200/20p: can be optioned to com0~com7 or pd0~pd7. all these are optioned by software. com8~com15 o lcd panel common outputs. vlcd i lcd driver power source. normal i/o pa0~pa7 i/o bidirectional 8-bit input/output ports. schmitt trigger input or cmos output. see mask option table for pull-high and wake-up function pb0~pb7 i/o bidirectional 8-bit input/output ports. schmitt trigger input or cmos output. see mask option table for pull-high function pd0~pd7 o or i/o bidirectional 8-bit input/output ports. schmitt trigger input and cmos output. ht95c300/30p: pd0~pd3 and pd4~pd7 can be per nibble optioned to seg36~seg39 and seg40~seg43 by software. HT95C200/20p: pd0~pd7 can be optioned to com0~com7 by software. see mask option table for pull-high function pe0~pe3 o or i/o bidirectional 4-bit input/output ports. schmitt trigger input and cmos output. ht95c300/30p: pe0~pe3 can be per nibble optioned to seg44~seg47 by software. HT95C200/20p: fixed for pe0~pe3. see mask option table for pull-high function dialer i/o (see the dialer i/o function ) hfi i schmitt trigger input structure. an external rc network is recommended for input debouncing. this pin is pulled low with internal resistance of 200k typ. hfo o cmos output structure. hdi i schmitt trigger input structure. an external rc network is recommended for input debouncing. this pin is pulled high with internal resistance of 200k typ. hdo o cmos output structure. hks i this pin detects the status of the hook-switch and its combination with hfi/hdi can con - trol the po pin output to make or break the line. po o cmos output structure controlled by hks and hfi/hdi pins and which determines whether the dialer connects or disconnects the telephone line. dnpo o nmos output structure. xmute o nmos output structure. usually, xmute is used to mute the speech circuit when trans - mitting the dialer signal. HT95C200/20p/300/30p rev. 0.10 5 october 1, 2002 preliminary
pin name i/o description peripherals dtmf o this pin outputs dual tone signals to dial out the phone number. the load resistor should not be less than 5k . music o this pin outputs the single tone that generated by the pfd generator. tip i input pin connected to the tip side of the twisted pair wires. it is internally biased to 1/2 vdd when the device is in power-up mode. this pin must be dc isolated from the line. ring i input pin connected to the ring side of the twisted pair wires. it is internally biased to 1/2 vdd when the device is in power-up mode. this pin must be dc isolated from the line. rdeti i this pin detects ring energy on the line through an attenuating network. rtime i/o schmitt trigger input and nmos output pin which functions with rdeti pin to make an rc network that performs ring detection function. lbin i this pin detects battery low through external r1/r2 to determine threshold voltage. absolute maximum ratings supply voltage ........................................ 0.3v to 5.5v storage temperature ........................... 50 cto125 c input voltage .............................. v ss 0.3 to v dd +0.3v operating temperature .......................... 25 cto70 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. electrical characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions cpu i idl idle mode current 5v 32768hz off, 3.58mhz off, cpu off, lcd off, wdt off, no load 2 a i slp sleep mode current 5v 32768hz on, 3.58mhz off, cpu off, lcd off, wdt off, no load 30 a i grn green mode current 5v 32768hz on, 3.58mhz off, cpu on, lcd off, wdt off, no load 50 a i nor normal mode current 5v 32768hz on, 3.58mhz on, cpu on, lcd on, wdt on, dtmf generator off, fsk decoder off, no load 3ma v il i/o port input low voltage 5v 0 1v v ih i/o port input high voltage 5v 4 5v i ol i/o port sink current 5v 46 ma i oh i/o port source current 5v 2 3 ma r ph pull-high resistor 5v 10 30 k v lbin low battery detection reference voltage 5v 1.10 1.15 1.20 v HT95C200/20p/300/30p rev. 0.10 6 october 1, 2002 preliminary
symbol parameter test conditions min. typ. max. unit v dd conditions lcd driver v lcd lcd panel power supply 35 v i lcd lcd operation current v lcd =5v, 32768hz, no load 100 a dialer i/o i xmo xmute leakage current 2.5v xmute pin=2.5v 1 a i olxm xmute sink current 2.5v xmute pin=0.5v 1 ma i hks hks input current 2.5v hks pin=2.5v 0.1 a r hfi hfi pull-low resistance 2.5v v hfi =2.5v 200 k r hdi hdi pull-high resistance 2.5v v hdi =0v 200 k i oh2 hfo source current 2.5v v oh =2v 1 ma i ol2 hfo sink current 2.5v v ol =0.5v 1 ma i oh3 hdo source current 2.5v v oh =2v 1 ma i ol3 hdo sink current 2.5v v ol =0.5v 1 ma i oh4 po source current 2.5v v oh =2v 1 ma i ol4 po sink current 2.5v v ol =0.5v 1 ma i ol5 dnpo sink current 2.5v v ol =0.5v 1 ma dtmf generator v tdc dtmf output dc level 0.45v dd 0.7v dd v v tol dtmf sink current v dtmf =0.5v 0.1 ma v tac dtmf output ac level row group, r l =5k 120 155 180 mvrms r l dtmf output load thd
23db 5 k a cr column pre-emphasis row group=0db 1 2 3 db thd tone signal distortion r l =5k 30 23 db fsk decoder input sensitivity: tip, ring 40 45 dbm transmission rate 5v 1188 1200 1212 baud s/n signal to noise ratio 20 db band-pass filter frequency response relative to 1700hz @ 0dbm
60hz 550hz 2700hz 3300hz 64 4 3 34 db carrier detect sensitivity 48 dbm t supd power up to fsk signal set up time 15 ms HT95C200/20p/300/30p rev. 0.10 7 october 1, 2002 preliminary
HT95C200/20p/300/30p rev. 0.10 8 october 1, 2002 preliminary functional description execution flow the system clock for the telephone controller is derived from a 32768hz crystal oscillator. a built-in frequency up conversion circuit provides dual system clock, namely; 32768hz and 3.58mhz. the system clock is internally divided into four non-overlapping clocks. one instruc - tion cycle consists of four system clock cycles. instruc - tion fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle. the pipelining scheme causes each instruction to be effec - tively executed in a instruction cycle. if an instruction changes the program counter, two instruction cycles are required to complete the instruction. program counter pc the program counter (pc) controls the sequence in which the instructions stored in the program rom are executed and its contents specify a full range of pro - gram memory. after accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by 1. the program counter then points to the memory word containing the next in - struction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set, internal interrupt, external interrupt or return from subroutine, the program counter manipulates the pro - gram transfer by loading the address corresponding to each instruction. the conditional skip is activated by in - structions. once the condition is met, the next instruc - tion, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed to the next in - struction. the program counter lower order byte register (pcl:06h) is a readable and write-able register. moving data into the pcl performs a short jump. the destina - 0 & * 0 & * 0 & * <
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HT95C200/20p/300/30p rev. 0.10 9 october 1, 2002 preliminary tion will be within 256 locations. when a control transfer takes place, an additional dummy cycle is required. program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 8192 16 bits, addressed by the program counter and ta - ble pointer. certain locations in the program memory are reserved for special usage: location 0000h this area is reserved for the initialization program. af - ter chip power-on reset or external reset or wdt time-out reset, the program always begins execution at location 0000h. location 0004h this area is reserved for the external interrupt service program. if the int /tmr1 input pin is activated, the external interrupt is enabled and the stack is not full, the program begins execution at location 0004h. location 0008h this area is reserved for the timer/event counter 0 in - terrupt service program. if a timer interrupt results from a timer/event counter 0 overflow, the timer/event counter 0 interrupt is enabled and the stack is not full, the program begins execution at loca - tion 0008h. location 000ch this location is reserved for the timer/event counter 1 interrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, the timer/event counter 1 interrupt is enabled and the stack is not full, the program begins execution at loca - tion 000ch. location 0010h this location is reserved for the peripherals interrupt service program. the peripherals include a dtmf generator and fsk decoder. when the dtmf genera - tor is operated in burst mode, it will generate an inter - rupt after 1 burst cycle is finished. when the fsk decoder detects a ringer or line reversal or fsk carrier signal or fsk packet data, the fsk interrupt is also generated. if these interrupts occurred, the peripheral interrupt is enabled and the stack is not full, the pro - gram begins execution at location 0010h. the pro - grammer could distinguish from these interrupts from the dtmfc and fsks register. location 0014h this location is reserved for real time clock (rtc) in- terrupt service program. when rtc generator is en- abled and time-out occurs, the rtc interrupt is enabled and the stack is not full, the program begins execution at location 0014h. location 0018h this location is reserved for the hks pin edge transi- tion or hdi pin falling edge transition or hfi pin rising edge transition. if this condition occurs, the dialer i/o interrupt is enabled and the stack is not full, the pro - gram begins execution at location 18h. table location any location in the rom space can be used as look-up tables. the instructions tabrdc [m] (the current page, one page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined, and the higher-order byte of the table word is transferred to tblh. the table instruction(s) table location *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p12 p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 note: *12~*0: table location bits p12~p8: current program counter bits @7~@0: table pointer bits ' ' ' 5 ' ' * 5 ' ' + 5 # "
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HT95C200/20p/300/30p rev. 0.10 10 october 1, 2002 preliminary pointer (tblp) is a read/write register (07h), which indi - cates the table location. before accessing the table, the location must be placed in the tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read in - struction used in the isr. errors will then occur. hence, simultaneously using the table read instruction in the main routine and the isr should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt is supposed to be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed-up. all table related instructions require two cycles to complete the operation. these areas may function as normal pro - gram memory depending on the requirements. stack register this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither read - able nor write-able. the activated level is indexed by the stack pointer (sp) and is neither readable nor write-able. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the pro- gram counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and an interrupt takes place, the interrupt request flag will be recorded but the acknowl- edge signal will be inhibited even if this interrupt is en- abled. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature pre - vents stack overflow allowing the programmer to use the structure more easily. if the stack is full and a call is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent eight return addresses are stored). data memory the data memory is divided into four functional groups: special function registers, embedded control register, lcd display memory and general purpose memory. most are read/write, but some are read only. the special function registers is located from 00h to 1fh. the embedded control register are located in the memory areas from 20h to 3fh. the remaining space which are not specified on the following table before the 40h are reserved for future expanded usage and read - ing these locations will get 00h . the general purpose data memory is divided into 11 banks (ht95c300/30p) or 6 banks (HT95C200/20p). the banks in the ram are all addressed from 40h to 0ffh and they are selected by setting the value of the bank pointer (bp). all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di - rectly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer registers (mp0 or mp1). the bank1~bank10 are only indirectly accessible through memory pointer 1 register (mp1). the lcd display memory is located at bank 1bh. they can be read and written to by the indirect addressing mode using memory pointer 1 (mp1). to turn the display on or off, a 1 or 0 is written to the corresponding bit of the memory area. special register, embedded control register, lcd display memory and general purpose ram bp address function description special function register 00 00 iar0 indirect addressing register 0 00 01 mp0 memory pointer register 0 00 02 iar1 indirect addressing register 1 00 03 mp1 memory pointer register 1 00 04 bp bank pointer register 00 05 acc accumulator 00 06 pcl program counter lower-order byte register 00 07 tblp table pointer 00 08 tblh table higher-order byte register 00 09 wdts watchdog timer option setting register 00 0a status status register 00 0b intc0 interrupt control register 0
HT95C200/20p/300/30p rev. 0.10 11 october 1, 2002 preliminary bp address function description 00 0c tmr0h timer/event counter 0 high-order byte register 00 0d tmr0l timer/event counter 0 low-order byte register 00 0e tmr0c timer/event counter 0 control register 00 0f tmr1h timer/event counter 1 high-order byte register 00 10 tmr1l timer/event counter 1 low-order byte register 00 11 tmr1c timer/event counter 1 control register 00 12 pa port a data register 00 13 pac port a control register 00 14 pb port b data register 00 15 pbc port b control register 00 16 dialerio dialer i/o register 00 18 pd port d data register 00 19 pdc port d control register 00 1a pe port e data register (bit3~bit0) 00 1b pec port e control register (bit3~bit0) 00 1e intc1 interrupt control register 1 embedded control register 00 20 dtmfc dtmf generator control register 00 21 dtmfd dtmf generator data register 00 22 line line control register 00 24 rtcc real time clock control register 00 26 mode operation mode control register 00 28 lcdio lcd segment and i/o option register 00 29 fskc fsk decoder control register 00 2a fsks fsk decoder status register 00 2b fskd fsk packet data register 00 2d lcdc lcd driver control register 00 2e pfdc pfd control register 00 2f pfdd pfd data register general purpose ram 00 40~ff bank0 ram general purpose ram space 01 40~ff bank1 ram general purpose ram space 02 40~ff bank2 ram general purpose ram space 03 40~ff bank3 ram general purpose ram space 04 40~ff bank4 ram general purpose ram space 05 40~ff bank5 ram general purpose ram space 06 40~ff bank6 ram general purpose ram space (ht95c300/30p only) 07 40~ff bank7 ram general purpose ram space (ht95c300/30p only) 08 40~ff bank8 ram general purpose ram space (ht95c300/30p only) 09 40~ff bank9 ram general purpose ram space (ht95c300/30p only) 0a 40~ff bank10 ram general purpose ram space (ht95c300/30p only)
HT95C200/20p/300/30p rev. 0.10 12 october 1, 2002 preliminary bp address function description lcd ram display memory 1b 40~57 lcd ram HT95C200/20p: lcd ram mapping space for com0~com7 1b 40~6f lcd ram ht95c300/30p: lcd ram mapping space for com0~com7 1b 70~87 lcd ram HT95C200/20p: lcd ram mapping space for com8~com15 1b 70~9f lcd ram ht95c300/30p: lcd ram mapping space for com8~com15 indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] will access the memory pointed to by mp0 and mp1, respectively. reading loca - tion [00h] or [02h] indirectly returns the result 00h, while writing it leads to no operation. mp0 is indirectly addressable in bank0, but mp1 is available for all banks by switch bp [04h]. if bp is unequal to 00h, the indirect addressing mode to read/write operation from 00h~3fh will return the result as same as the value of bank0. the memory pointer registers mp0 and mp1 are 8-bits registers, and the bank pointer register bp is 5-bits reg - ister. accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and can operate with immediate data. all data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera- tions and provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz, etc.) the alu not only saves the results of a data operation but also changes the status register. status register status this status register contains the carry flag (c), auxiliary carry flag (ac), zero flag (z), overflow flag (ov), power down flag (pd), and watchdog time-out flag (to). it also records the status information and controls the opera - tion sequence. except for the to and pd flags, bits in the status register can be altered by instructions, similar to the other regis - ters. data written into the status register will not change the to or pd flag. operations related to the status regis - ter may yield different results from those intended. the to flag can be affected only by system power-up, a wdt time-out or executing the clr wdt or halt instruction. the pd flag can be affected only by execut- ing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. on entering the interrupt sequence or executing the subroutine call, the status register will not be automati- cally pushed onto the stack. if the contents of the status are important and if the sub - routine can corrupt the status register, precautions must be taken to save it. register label bits function status (0ah) c0 c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. also it is affected by a rotate through carry instruction. ac 1 ac is set if the operation results in a carry out of the low nibbles in addition or no bor - row from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z 2 z is set if the result of an arithmetic or logic operation is 0; otherwise z is cleared. ov 3 ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pd 4 pd is cleared when either a system power-up or executing the clr wdt instruc - tion. pd is set by executing the halt instruction. to 5 to is cleared by a system power-up or executing the clr wdt or halt instruc - tion. to is set by a wdt time-out. 6, 7 unused bit, read as 0
HT95C200/20p/300/30p rev. 0.10 13 october 1, 2002 preliminary interrupt the telephone controller provides an external interrupt, internal timer/event counter interrupt, a peripheral inter - rupt, an internal real time clock interrupt and internal di - aler i/o interrupt. the interrupt control registers 0 and interrupt control register 1 both contains the interrupt control bits that set the enable/disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in - terrupts will be blocked (by hardware clearing the emi bit). this scheme may prevent any further interrupt nest - ing. other interrupt requests may occur during this inter - val but only the interrupt request flag is recorded. if a certain interrupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc0 (intc1) may be set to allow interrupt nesting. if the stack is full, any other interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate ser - vice is desired, the stack must be prevented from be - coming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro- gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. external interrupt is triggered by a high to low transition of the int /tmr1 pin and the interrupt request flag eif will be set. when the external interrupt is enabled, the stack is not full and the external interrupt is active, a sub - routine call to location 04h will occur. the interrupt re - quest flag eif and emi bits will be cleared to disable other interrupts. the timer/event counter 0 interrupt is generated by a timeout overflow and the interrupt request flag t0f will be set. when the timer/event counter 0 interrupt is en - abled, the stack is not full and the t0f bit is set, a sub - routine call to location 08h will occur. the interrupt request flag t0f and emi bits will be cleared to disable further interrupts. the timer/event counter 1 interrupt is generated by a timeout overflow and the interrupt request flag t1f will be set. when the timer/event counter 1 interrupt is en - abled, the stack is not full and the t1f bit is set, a sub - routine call to location 0ch will occur. the interrupt request flag t1f and emi bits will be cleared to disable further interrupts. the peripheral interrupt is activated when the burst-cycle is finished or the fsk decoder detect the ring signal or line reversal or fsk carrier signal or fsk packet data. when these interrupts occurred, the inter - rupt request flag perf will be set. when the peripheral interrupt is enabled, the stack is not full and the perf is set, a subroutine call to location 10h will occur. the in - terrupt request flag perf and emi bits will be cleared to disable other interrupts. the real time clock interrupt is generated by a 1hz rtc generator. when the rtc time-out occurs, the interrupt request flag rtcf will be set. when the rtc interrupt is enabled, the stack is not full and the rtcf is set, a sub- routine call to location 14h will occur. the interrupt re- quest flag rtcf and emi bits will be cleared to disable other interrupts. register label bits r/w function intc0 (0bh) emi 0 rw controls the master (global) interrupt (1=enabled; 0=disabled) eei 1 rw controls the external interrupt (1=enabled; 0=disabled) et0i 2 rw controls the timer/event counter 0 interrupt (1=enabled; 0=disabled) et1i 3 rw controls the timer/event counter1 interrupt (1=enabled; 0=disabled) eif 4 rw external interrupt request flag (1=active; 0=inactive) t0f 5 rw timer/event counter 0 request flag (1=active; 0=inactive) t1f 6 rw timer/event counter1 request flag (1=active; 0=inactive) 7ro unused bit, read as 0 intc1 (1eh) eperi 0 rw control the peripheral interrupt (1=enable; 0=disable) ertci 1 rw control the real time clock interrupt (1=enable; 0=disable) edri 2 rw control the dialer i/o interrupt (1=enable; 0=disable) 3ro unused bit, read as 0 perf 4 rw peripheral interrupt request flag (1=active; 0=inactive) rtcf 5 rw internal real time clock interrupt request flag (1=active; 0=inactive) drf 6 rw internal dialer i/o interrupt request flag (1=active: 0=inactive) 7ro unused bit, read as 0
HT95C200/20p/300/30p rev. 0.10 14 october 1, 2002 preliminary the dialer i/o interrupt is triggered by any edge transi - tion onto hks pin or a falling edge transition onto hdi pin or a rising edge transition onto hfi pin, the interrupt request flag drf will be set. when the dialer i/o inter - rupt is enabled, the stack is not full and the drf is set, a subroutine call to location 18h will occur. the interrupt request flag drf and emi bits will be cleared to disable other interrupts. during the execution of an interrupt subroutine, other in - terrupt acknowledge signals are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an interrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 1 04h timer/event counter 0 interrupt 2 08h timer/event counter 1 interrupt 3 0ch peripheral interrupt 4 10h real time clock interrupt 5 14h dialer i/o interrupt 6 18h priority of the interrupt emi, eei, et0i, et1i, eperi, ertci and edri are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupt from being serviced. once the interrupt request flags (eif, t0f, t1f, perf, rtcf, drf) are set by hardware or soft - ware, they will remain in the intc0 or intc1 registers until the interrupts are serviced or cleared by a software instruction. it is recommended that a program should not use the call subroutine within the interrupt subroutine. inter - rupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be dam - aged once the call operates in the interrupt subrou - tine. oscillator configuration there are two oscillator circuits in the controller, the ex - ternal 32768hz crystal oscillator and internal wdt osc. the 32768hz crystal oscillator and frequency-up con - version circuit (32768hz to 3.58mhz) are designed for dual system clock source. it is necessary for frequency conversion circuit to add external rc components to make up the low pass filter that stabilize the output fre - quency 3.58mhz (see the oscillator circuit). the wdt osc is a free running on-chip rc oscillator, and no external components are required. even if the system enters the idle mode (the system clock is stopped), the wdt osc still works within a period of 78 s normally. when the wdt is disabled or the wdt source is not this rc oscillator, the wdt osc will be disabled. watchdog timer wdt the wdt clock source is implemented by a wdt osc or external 32768hz or an instruction clock (system clock divided by 4), determined by the mask option. this timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with un- predictable results. the watchdog timer can be dis- abled by mask option. if the watchdog timer is disabled, all the executions related to the wdt result in no opera- tion. if the device operates in a noisy environment, using the on-chip wdt osc or 32768hz crystal oscillator is strongly recommended. when the wdt clock source is selected, it will be first di - vided by 512 (9-stage) to get the nominal time-out pe - riod. by invoking the wdt prescaler, longer time-out periods can be realized. writing data to ws2, ws1, ws0 can give different time-out periods. the wdt osc period is 78 s. this time-out period may vary with temperature, vdd and process variations. the wdt osc always works for any operation mode. 0 % 9 & % ' system oscillator circuit
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HT95C200/20p/300/30p rev. 0.10 15 october 1, 2002 preliminary if the instruction clock is selected as the wdt clock source, the wdt operates in the same manner except in the sleep mode or idle mode. in these two modes, the wdt stops counting and lose its protecting purpose. in this situation the logic can only be re-started by external logic. if the wdt clock source is the 32768hz, the wdt also operates in the same manner except in the idle mode. when in the idle mode, the 32768hz stops, the wdt stops counting and lose its protecting purpose. in this situation the logic can only be re-started by external logic. the high nibble and bit3 of the wdts are reserved for user defined flags, which can be used to indicate some specified status. the wdt time-out under normal mode or green mode will initialize chip reset and set the status bit to . but in the sleep mode or idle mode, the time-out will initial- ize a warm reset and only the program counter and stack pointer are reset to 0. to clear the wdt contents (including the wdt prescaler), three methods are adopted; external reset (a low level to res pin), soft - ware instruction and a halt instruction. the software instruction include clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one can be active depending on the mask option wdt instr .ifthe clr wdt is se - lected (i.e. one clear instruction), any execution of the clr wdt instruction will clear the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e. two clear instructions), these two instructions must be exe - cuted to clear the wdt; otherwise, the wdt may reset the chip as a result of time-out. controller operation mode holtek s telephone controllers support two system clock and four operation modes. the system clock could be 32768hz or 3.58mhz and operation mode could be nor- mal, green, sleep or idle mode. these are all selected by the software. the following conditions will force the operation mode to change to green mode: register label bits r/w function wdts (09h) ws0 ws1 ws2 0 1 2 rw watchdog timer division ratio selection bits bit 2, 1, 0=000, division ratio=1:1 bit 2, 1, 0=001, division ratio=1:2 bit 2, 1, 0=010, division ratio=1:4 bit 2, 1, 0=011, division ratio=1:8 bit 2, 1, 0=100, division ratio=1:16 bit 2, 1, 0=101, division ratio=1:32 bit 2, 1, 0=110, division ratio=1:64 bit 2, 1, 0=111, division ratio=1:128 7~3 rw unused bit. these bits are read/write-able. register label bits r/w function mode (26h) 4~0 ro unused bit, read as 0 upen 5 rw 1: enable frequency up conversion function to generate 3.58mhz 0: disable frequency up conversion function to generate 3.58mhz mode0 6 rw 1: disable 32768hz oscillator while the halt instruction is executed (idle mode) 0: enable 32768hz oscillator while the halt instruction is executed (sleep mode) mode1 7 rw 1: select 3.58mhz as cpu system clock 0: select 32768hz as cpu system clock operation mode description halt instruction mode1 mode0 upen operation mode 32768hz 3.58mhz system clock not execute 1 x 1 normal on on 3.58mhz not execute 0 x 0 green on off 32768hz be executed 0 0 0 sleep on off halt be executed 0 1 0 idle off off halt note: x means don t care
HT95C200/20p/300/30p rev. 0.10 16 october 1, 2002 preliminary any reset condition from any operation mode any interrupt from sleep mode or idle mode port a wake-up from sleep mode or idle mode how to change the operation mode normal mode to green mode: clear mode1 to 0, then operation mode is changed to green mode but the upen status is not changed. however, upen can be cleared by software. normal mode or green mode to sleep mode: step 1: clear mode0 to 0 step 2: execute halt instruction after step 2, operation mode is changed to sleep mode, the upen and mode1 are cleared to 0 by hardware. normal mode or green mode to idle mode: step 1: set mode0 to 1 step 2: execute halt instruction after step 2, operation mode is changed to idle mode, the upen and mode1 are cleared to 0 by hardware. green mode to normal mode: step 1: set upen to 1 step 2: software delay 20ms at least step 3: set mode1 to 1 after step 3, operation mode is changed to normal mode. sleep mode or idle mode to green mode: method 1: any reset condition occurred method 2: any interrupt is active method 3: port a wake-up note the timer0, timer1, rtc and dialer i/o inter- rupt function will not work at the idle mode be- cause the 32768hz crystal is stopped. the reset conditions include power on reset, external re - set, wdt time-out reset. by examining the processor status flag, pd and to, the program can distinguish be - tween different reset conditions . refer to the reset function for detailed description. the port a wake-up and interrupt can be considered as a continuation of normal execution. each bit in port a can be independently selected to wake-up the device by mask option. awakening from port a stimulus, the pro - gram will resume execution of the next instruction. any valid interrupts from sleep mode or idle mode may cause two sequences. one is if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruc - tion. the other is if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. it is necessary to mention that if an interrupt request flag is set to 1 before entering the sleep mode or idle mode, the wake-up function of the related interrupt will be dis - abled. once a sleep mode or idle mode wake-up event occurs, it will take sst delay time (1024 system clock period) to resume to green mode. in other words, a dummy period is inserted after a wake-up. if the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cy - cles. if the wake-up results in the next instruction execu - tion, this will be executed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the sleep mode or idle mode. the sleep mode or idle mode is initialized by the halt instruction and results in the following. the system clock will be turned off. the wdt function will be disabled if the wdt clock source is the instruction clock. the wdt function will be disabled if the wdt clock source is the 32768hz in idle mode. the wdt will still function if the wdt clock source is the wdt osc. if the wdt function is still enabled, the wdt counter and wdt prescaler will be cleared and recounted again. the contents of the on chip ram and registers remain unchanged. all the i/o ports maintain their original status. the flag pd is set and the flag to is cleared by hard- ware. reset there are three ways in which a reset can occur. power on reset. a low pulse onto res pin. wdt time-out. after these reset conditions, the program counter and stack pointer will be cleared to 0. to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem is reset or awakes from the sleep or idle operation mode. > ; ' ' 9 ' ? < reset circuit
HT95C200/20p/300/30p rev. 0.10 17 october 1, 2002 preliminary by examining the processor status flags pd and to, the software program can distinguish between the different chip resets . to pd reset condition 0 0 power on reset uu external reset during normal mode or green mode 01 external reset during sleep mode or idle mode 1u wdt time-out during normal mode or green mode 11 wdt time-out during sleep mode or idle mode note: u means unchanged the functional units chip reset status are shown below: program counter 000h interrupt disabled prescaler cleared wdt cleared after a master reset, wdt begins counting. (if wdt function is enabled by mask option) timer/event counter 0/1 off input/output port input mode stack pointer points to the top of the stack 7 "
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reset timing chart when the reset conditions occurred, some registers may be changed or unchanged. register addr. reset conditions power on res pin res pin (sleep/idle) wdt wdt (sleep/idle) iar0 00h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp0 01h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu iar1 02h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 03h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 04h ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---u uuuu acc 05h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu pcl 06h 0000h 0000h 0000h 0000h 0000h tblp 07h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh 08h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 09h 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status 0ah --00 xxxx --uu uuuu --01 uuuu --1u uuuu --11 uuuu intc0 0bh -000 0000 -000 0000 -000 0000 -000 0000 uuuu uuuu tmr0h 0ch xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0l 0dh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 0eh 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- tmr1h 0fh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr1l 10h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
HT95C200/20p/300/30p rev. 0.10 18 october 1, 2002 preliminary register addr. reset conditions power on res pin res pin (sleep/idle) wdt wdt (sleep/idle) tmr1c 11h 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- pa 12h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 13h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 14h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 15h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu dialerio 16h 111x xxxx 111x xxxx 111x xxxx 111x xxxx uuuu uuuu pd 18h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 19h 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pe 1ah ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu pec 1bh ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu intc1 1eh -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu dtmfc 20h -0-0 1001 -0-0 1001 -0-0 1001 -0-0 1001 -u-u uuuu dtmfd 21h 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu line 22h 0--- ---- u--- ---- u--- ---- u--- ---- u--- ---- rtcc 24h 0-0- ---- u-u- ---- u-u- ---- u-u- ---- u-u- ---- mode 26h 000- ---- 00u- ---- 000- ---- 00u- ---- 000- ---- lcdio 28h 000- ---- uuu- ---- uuu- ---- uuu- ---- uuu- ---- fskc 29h --11 11-1 --11 11-1 --11 11-1 --11 11-1 --uu uu-u fsks 2ah -x0- 1100 -x0- 1100 -x0- 1100 -x0- 1100 -xu- uuuu fskd 2bh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu lcdc 2dh 0000 -000 uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu pfdc 2eh 0000 ---- 0000 ---- 0000 ---- 0000 ---- uuuu ---- pfdd 2fh 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu ram (data & lcd) x u u u u note: u means unchanged x means unknown - means unused
HT95C200/20p/300/30p rev. 0.10 19 october 1, 2002 preliminary timer/event counter two timer/event counters (tmr0, tmr1) are imple - mented in the telephone controller series. the timer/event counter 0 and timer/event counter 1 con - tain 16-bits programmable count-up counter and the clock may come from an external source or internal source. for tmr0 internal source is instruction clock (system clock/4). for tmr1 internal source is 32768hz. using the 32768hz clock or instruction clock, there is only one reference time-base. the external clock input allows the user to count external events, measure time intervals or pulse width, or generate an accurate time base. there are 3 registers related to timer/event counter 0; tmr0h, tmr0l, tmr0c. writing tmr0l only writes the data into a low byte buffer, but writing tmr0h simul - taneously writes the data along with the contents of the low byte buffer into the timer/event counter 0 preload register (16-bit). the timer/event counter 0 preload register is changed by writing tmr0h operations. writ - ing tmr0l will keep the timer/event counter 0 preload register unchanged. reading tmr0h latches the tmr0l into the low byte buffer to avoid a false timing problem. reading tmr0l returns the contents of the low byte buffer. in other words, the low byte of the timer/event counter 0 can not be read directly. it must read the tmr0h first to make the low byte contents of timer/event counter 0 be latched into the buffer. there are 3 registers related to the timer/event counter 1; tmr1h, tmr1l, tmr1c. the timer/event counter 1 operates in the same manner as the timer/event counter 0. the tmr0c is the timer/event counter 0 control regis - ter, which defines the timer/event counter 0 options. the timer/event counter 1 has the same options as the timer/event counter 0 and is defined by tmr1c. the timer/event counter control registers define the operat - ing mode, counting enable or disable and active edge. ' ( ' ; ' 8 " 7

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HT95C200/20p/300/30p rev. 0.10 20 october 1, 2002 preliminary the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr0 or int/ tmr1) pin. the timer mode functions as a normal timer with the clock source coming from in - struction clock (tmr0) or 32768hz (tmr1). the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr0 or int/ tmr1). the counting is based on the 32768hz clock for tmr1 or instruction clock for tmr0. in the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to ffffh. if an over - flow occurs, the counter is reloaded from the timer/event counter preload register and generates the correspond - ing interrupt request flag (t0f/t1f) at the same time. in pulse width measurement mode with the ton and te bits equal to 1, once the tmr0/tmr1 pin has received a transient from low to high (or high to low; if the te bit is 0) it will start counting until the tmr0/tmr1 pin returns to the original level and resets the ton. the measured result will remain in the timer/event counter even if the activated transient occurs again. in other words, only 1 cycle measurement can be done. until setting the ton, the cycle measurement will function again as long as it receives further transient pulse. note that, in this operat- ing mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload register and continue to measure the width and issues the inter- rupt request just like the other two modes. to enable the counting operation, the timer on bit (ton) should be set to 1. in the pulse width measurement mode, the ton will be cleared automatically after the measurement cycle is completed. but in the other two modes the ton can only be reset by instruction. the overflow of the timer/event counter is one of the wake-up sources. no matter what the operation mode is, writin ga0to et0i/et1i can disable the correspond - ing interrupt service. in the case of timer/event counter off condition, writing data to the timer/event counter preload register also re - loads that data to the timer/event counter. but if the timer/event counter is turned on, data written to the timer/event counter is reserved only in the timer/event counter preload register. the timer/event counter will go on operating until an overflow occurs. input/output ports there are 28 bidirectional input/output lines in the tele - phone controller, labeled as pa, pb, pd and pe. all of these i/o ports can be used for input and output opera - tions. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 18h or 1ah). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pdc, pec) to control the input/output configuration. with this control register, cmos output or schmitt trig - ger input can be reconfigured dynamically under soft - ware control. to make one i/o line to function as an input line, the corresponding latch of the control register must be written with a 1 . the pull-high resistance shows itself automatically if the pull-high option is se - lected. the input source also depends on the control register. if the control register bit is 1 , the input will read the pad state. if the control register bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in the read-modify-write instruction. for output function, cmos is the only configuration. each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h, 18h or 1ah) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. they are selected by mask option per bit. there is a pull-high option available for all i/o lines. once the pull-high option of an i/o line is selected, the i/o lines have pull-high resistor. otherwise, the pull-high resistor is absent. it should be noted that a non-pull-high i/o line operating in input mode may cause a floating state. i/o port pull-high, wake-up function are selected by mask option i/o port output input pull-high resistor wake-up function pa cmos selected per bit selected per bit pb cmos selected per bit x pd cmos ht95c300/30p: selected per nibble HT95C200/20p: selected per byte x pe cmos selected per nibble x note: x: unavailable for the ht95c300/30p, the pd0~pd7 and seg36~seg43 share the same pads. the pe0~pe3 and seg44~seg47 share the same pads. they can be selected per nibble by software option at any time.
HT95C200/20p/300/30p rev. 0.10 21 october 1, 2002 preliminary for the HT95C200/20p, the pd0~pd7 and com0~com7 share the same pads. they can only be selected per byte by software option at any time. when the pd0~pd7 or the pe0~pe3 are not selected, the i/o port control register (19h), pec (1bh) could be read/write-able and be used as a general user ram, but this function is not available for register pd (18h) and pe (1ah). fsk decoder the fsk decoder supports three interrupt sources to the peripheral interrupt vector. there are ring detect or line reversal detect, fsk carrier detect and fsk packet data. write 0 to the control flag, rmsk, cmsk and fmsk will enable these interrupt. when any of these in- terrupt occurs, its interrupt flag (rdetf, cdetf, fskf) will be set to 1 by hardware even if the interrupt is dis - abled. these interrupts will cause a peripheral interrupt if the peripheral interrupt is enabled.when the periph - eral interrupt occurs, the interrupt request flag perf will be set and a subroutine call to location 10h will occur. returning from the interrupt subroutine, the interrupt flag rdetf, cdetf or fskf will not be cleared by hardware, the user should clear it by software. if inter- rupt flag rdetf is not cleared, next ring detect interrupt will be inhibited, other interrupt flags cdetf, fskf have the same behavior. the power down mode (f_pwdn=1) will terminate all the fsk decoder func- tion, however, the registers fskc, fsks and fskd are accessible at this power down mode. register label bits r/w function lcdio (28h) 0~4 ro unused bit, read as 0 spe0 5 rw for ht95c300/30p only 0: seg44~seg47 pins are lcd segment output 1: seg44~seg47 pins are pe0~pe3 pins spd0 6 rw for ht95c300/30p only 0: seg36~seg39 pins are lcd segment output 1: seg36~seg39 pins are pd0~pd3 pins spd1 7 rw for ht95c300/30p only 0: seg40~seg43 pins are lcd segment output 1: seg40~seg43 pins are pd4~pd7 pins lcdc (2dh) vbias 1 rw for ht95c300/30p 0: com0~com7 are lcd common output 1: com0~com7 are unused pin for HT95C200/20p 0: com0~com7 are lcd common output 1: com0~com7 are pd0~pd7 pins register label bits r/w function fskc (29h) f_pwdn 0 rw fsk decoder power down 1: fsk decoder is at power down mode 0: fsk decoder is at operation mode 1ro unused bit, read as 0 fmsk 2 rw fsk packet data interrupt mask 1: disable fsk packet data interrupt 0: enable fsk packet data interrupt rmsk 3 rw ring or line reversal detect interrupt mask 1: disable ring or line reversal detect interrupt 0: enable ring or line reversal detect interrupt cmsk 4 rw carrier detect interrupt mask 1: disable carrier detect interrupt 0: enable carrier detect interrupt fsksel 5 rw select fsk packet data source 1: fsk packet data source is doutc 0: fsk packet data source is dout 6, 7 ro unused bit, read as 0
HT95C200/20p/300/30p rev. 0.10 22 october 1, 2002 preliminary register label bits r/w function fsks (2ah) rdetf 0 rw ring or line reversal detect interrupt flag 1: ring or line reversal detected 0: no ring or line reversal detected this flag is set by hardware and cleared by software. cdetf 1 rw fsk carrier detect interrupt flag 1: an fsk carrier signal is detected 0: no valid fsk carrier signal is detected this flag is set by hardware and cleared by software. dout 2 ro this flag presents the fsk decoder output when the decoder is at op - eration mode. this data stream includes the alternate 1 and 0 pattern, the marking and the data. doutc 3 ro this flag present the fsk decoder output like as the dout flag but does not include the alternate 1 and 0 pattern. 4ro unused bit, read as 0 fskf 5 rw fsk packet data interrupt flag 1: fsk packet data is ready 0: fsk packet data is not ready this flag is set by hardware and cleared by software. ringf 6 ro this flag presents the ring coming signal. refer to the following figure. 7ro unused bit, read as 0 fskd (2bh) 7~0 ro fsk packet data register ; < e ; > ;

3 9 ring or line reversal detect when no signal is present on the telephone line, rdeti will be at gnd and rtime is pulled to vdd by r1. if a line reversal occurs, the rdeti pin will become high. this causes rtime and internal signal r_det to be pulled low. the c1 and r1 ensure that the r_det sig- nal is low during such a time, so that processor can de- tect it. when a ring occurs on the line, internal signal r_det is permanently low, indicating the envelope of the ring. if the frequency of the ring must be measured, c1 may be removed, rtime and r_det inverter follow rdeti. the flag rdetf will go high when the r_det signal falling edge is detected. this may cause a peripheral in - terrupt if rmsk is 0 and the peripheral interrupt is en - abled (eperi=1). fsk data output the fsk decoder will decode the fsk signal on the tip and ring line and produce two kinds of data formats, the serial data and the 8-bit packet data. it also provides the fsk carrier detection signal. to enable the fsk decoder, the f_pwdn should be written as 0. once the fsk carrier signal is detected, the flag cdetf will be set to 1. this may cause a peripheral interrupt if cmsk is 0 and the peripheral interrupt is en- abled. the serial fsk data is present in two formats: raw data and cook data, and could be monitored by the flag dout, doutc, respectively. the flag dout presents the output of the decoder when the decoder is at operation mode. this data stream in - cludes the alternate 1 and 0 pattern, the marking and the data.
HT95C200/20p/300/30p rev. 0.10 23 october 1, 2002 preliminary the flag doutc presents the output of the decoder when the decoder is at operation mode. this data stream is like the dout flag but does not include the al - ternate 1 and 0 pattern. if the fsk data is not detected, the dout and doutc are held high. beside the serial data, the decoder also provides fsk packet data. when decoder receives an fsk signal, it will packet 10 bits data to 8 bits data, the first and 10th bits will be discarded. when the 8-bit packet data is valid, it will be stored in the fsk data register fskd, the fsk packet data interrupt flag fskf will be set to 1. this may cause a peripheral interrupt if fmsk is 0 and the peripheral interrupt is enabled. the fsk packet source could be dout or doutc, selected by fsksel. note that the start bit of the 10 packet bit should be 0, so the mark signal (one of the fsk data signals) will not be packeted. to detect the carrier signal or decode the serial data or packet 10-bit data to 8-bit data, the operation mode of the controller must be selected in normal mode (proces - sor running with 3.58mhz). when the operation mode is green or sleep, fsk decoder will decode the wrong sig - nal. however, when the operation mode is green or sleep mode and the fsk decoder is at power down mode (f_pwdn=1), the ring and line reversal detect is still functional. dtmf generator the dtmf (dual tone multiple-frequency) signal gen - erator is implemented in the telephone controller. it can generate 16 dual tones and 8 single tones from the dtmf pin. this generators also support power down, tone on/off, burst mode function. the dtmf generator clock source is 3.58mhz, before using this function, the system operation mode must be at normal mode. the generator supports one interrupt source to the pe- ripheral interrupt vector, namely dtmf burst-cycle inter- rupt. write 0 to the control flag, bmsk will enable this interrupt. when the dtmf generator finishes 1 burst-cycle, the interrupt flag burstf will be set to 1 by hardware even if the interrupt is disabled. this interrupt will cause a peripheral interrupt if the peripheral interrupt is enabled. when the peripheral interrupt occurs, the in - terrupt request flag perf will be set and a subroutine call to location 10h will occur. return from the interrupt subroutine, the interrupt flag burstf will not be cleared by hardware, the user could clear it by software if necessary. if this flag is not cleared, next burst inter - rupt will occur. the power down mode (d_pwdn=1) will terminate all the dtmf generator function, however, the registers dtmfc and dtmfd are accessible at this power down mode. " 8 ' ' ' ? ? ? ? ? ? < 1 " f " % % ? ? ? ? ? ? " 8 9 " 8 " 8 + a c
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HT95C200/20p/300/30p rev. 0.10 24 october 1, 2002 preliminary the dtmf pin output is controlled by the combination of the d_pwdn, tone, tr~tc value. control register bits dtmf pin output status d_pwdn tone tr4~tr1/tc4~tc1 1x x 0 0 0 x 1/2 vdd 0 1 0 1/2 vdd 0 1 any valid value 16 dual tones or 8 signal tones, bias with 1/2 vdd register label bits r/w function dtmfc (20h) d_pwdn 0 rw dtmf generator power down 1: dtmf generator is at power down mode. 0: dtmf generator is at operation mode. 1ro unused bit, read as 0 tone 2 rw tone output enable 1: dtmf signal output is enabled. 0: dtmf signal output is disabled. bmsk 3 rw burst-cycle interrupt mask 1: no interrupt will occur when 1 burst-cycle is finished. 0: an interrupt will occur when 1 burst-cycle is finished. this flag is functional only at burst-mode . burst 4 rw burst-mode bit 1: enable burst-mode. 0: disable burst-mode. 5ro unused bit, read as 0 burstf 6 rw burst-cycle interrupt flag 1: one burst-cycle is finished. 0: no burst-cycle is finished. this flag is set by hardware and cleared by software. this flag is functional only at burst-mode. 7ro unused bit, read as 0 dtmfd (21h) tc4~tc1 3~0 rw to set high group frequency tr4~tr1 7~4 rw to set low group frequency the dtmf generator supports two output modes, namely tone-mode and burst-mode. tone-mode: (d_pwdn=0, tone=1 and burst=0). the duration of tone-mode output should be handled by the software. dtmfd register value could be changed as desired, the dtmf pin will output the new dual-tone simulta - neously. bmsk and burstf flags are not necessary. any time set burst flag to 1, the dtmf output mode will be changed to burst-mode, and burst-cycle is starting. burst-mode: (d_pwdn=0, tone=1 and burst=1). the timing of burst-mode output is controlled by hard - ware. how to start the burst-mode at tone-mode, set burst flag to 1. if d_pwdn flag=0 & tone flag=0, set burst flag=1, then set tone flag=1. if d_pwdn flag=1, set burst flag & tone flag=1, then clear d_pwdn flag=0. the burst-cycle processing: step 1: dtmf pin automatically generates dtmf tone (determined by the tc~tr register value) for 82.5ms. step 2: dtmf pin automatically generates 1/2 vdd for 85.5ms. step 3: after the 85.5ms timeout, the tc~tr value is cleared to 0 by hardware. step 4: one burst-cycle is finished. the dtmf burst-cycle interrupt is generated. step 5: jump to step 1 for the next burst-cycle.
HT95C200/20p/300/30p rev. 0.10 25 october 1, 2002 preliminary precaution must be taken during burst-mode operation: dtmf pin will output 1/2 vdd during next burst-cycle if the user does not initialize the tc~tr value again. when the burst-cycles starts, if the user clears the burst flag to 0 before step 2 is finished, step 3 and step 4 will be executed and after step 4 is executed, dtmf output mode will be changed to tone-mode. when the burst-cycle starts, if the user clears the burst flag to 0 after step 3 is executed, then step 4 and step 5 will be executed. after next step 4 is exe - cuted, dtmf output mode will be changed to tone-mode. when the burst-cycles starts, if the user clears the tone flag to 0, dtmf output will be changed to 1/2 vdd. when the burst-cycle starts, if the user changes the tc~tr value at step1, dtmf pin output will also be changed (determined by the new tr~tc value). the dtmf output duration of burst-cycle is constantly 82.5ms. when the burst-cycle starts, if the user changes the tc~tr value at step2, dtmf pin still outputs 1/2 vdd. the dtmf output duration of burst-cycle is con - stantly 85.5ms. if the next burst-cycle is executed continuously, step 4 and step 5 occur simultaneously. ( 0 " > ; g 8 8 "
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: g dtmf burst_mode tone frequency output frequency (hz) % error specified actual 697 699 +0.29% 770 766 0.52% 852 847 0.59% 941 948 +0.74% 1209 1215 +0.50% 1336 1332 0.30% 1477 1472 0.34% % error does not contain the crystal frequency shift
HT95C200/20p/300/30p rev. 0.10 26 october 1, 2002 preliminary dtmf frequency selection table: register dtmfd[21h] low group high group dtmf output dtmf code tr4 tr3 tr2 tr1 tc4 tc3 tc2 tc1 low high 00010001697 1209 1 00010010697 1336 2 00010100697 1477 3 00011000697 1633 a 00100001770 1209 4 00100010770 1336 5 00100100770 1477 6 00101000770 1633 b 01000001852 1209 7 01000010852 1336 8 01000100852 1477 9 01001000852 1633 c 10000001941 1209 * 10000010941 1336 0 10000100941 1477 # 10001000941 1633 d single tone for testing only 00010000697 00100000770 01000000852 10000000941 00000001 1209 00000010 1336 00000100 1477 00001000 1633 writing other values to tr4~tr1, tc4~tc1 may generate an unpredictable tone.
HT95C200/20p/300/30p rev. 0.10 27 october 1, 2002 preliminary dialer i/o function a special dialer i/o circuit is built into the telephone controller for dialing application. these specially designed i/o cells allows the controller to work under a low voltage condition that usually happens when the subscriber s loop is long. dialer i/o pin function: name i/o description xmute nmos output xmute pin output is controlled by software. this is an nmos open drain structure pulled to vss during dialing signal transmission. otherwise, it is an open circuit. xmute is used to mute the speech circuit when transmitting the dialer signal. dnpo nmos output dnpo pin is an nmos output, usually by means of software to make/break the line. this pin is only controlled by software. po cmos output this pin is controlled by the hks , hfi and hdi pins. when po pin is high, the telephone line is make. when po pin is low, the telephone line is break. hks schmitt trigger input this pin controls the po pin directly. this pin is used to monitor the status of the hook-switch and its combination with hfi/hdi can control the po pin output to make or break the line. a rising edge to hks pin will cause the dialer i/o to be on-hook status and generate an interrupt, its vector is 18h. a falling edge to hks pin will cause the dialer i/o to be off-hook status and clear hfo and hdo flags to 0. this falling edge will also generate an interrupt, its vector is 18h. hdo cmos output this pin is controlled directly by hdi , hks and hfi pin. when hdo pin is high, the hold-line function is enabled and po outputs a high signal to make the line. hdi schmitt trigger input a low pulse to hdi pin (hold-line function request) will clear hfo to 0 and toggle hdo and generates an interrupt, its vector is 18h. this pin controls the hfo and hdo pins directly. this pin is functional only when the line is made, that is, off-hook or hand-free (po output high signal). hfo cmos output this pin is controlled directly by hfi, hdi and hks pins. when hfo pin is high, the hand-free function is enabled and po outputs a high sig- nal to make the line. hfi schmitt trigger input a high pulse to hfi pin (hand-free function request) will clear hdo to 0 and toggle hfo and generates an interrupt, its vector is 18h. this pin controls the po , hfo and hdo pins directly. the following are the recommended circuit for hfi and hdi pins. > ' ? < 5 < " ' 9 > ' ? < 5 " ' 9
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HT95C200/20p/300/30p rev. 0.10 28 october 1, 2002 preliminary phone controller also supports the dialer i/o flag to monitor the dialer status. register label bits r/w function dialerio (16h) hfi 0 ro 1: the hfi pin level is 1. 0: the hfi pin level is 0. hfo 1 ro 1: the hfo pin level is 1. 0: the hfo pin level is 0. hdi 2ro 1: the hdi pin level is 1. 0: the hdi pin level is 0. hdo 3 ro 1: the hdo pin level is 1. 0: the hdo pin level is 0. hks 4ro 1: the hks pin level is 1. 0: the hks pin level is 0. spo 5 rw 1: the po pin is controlled by the combination of the hks , hfi and hdi pin. 0: the po pin level is set to 0 by software. sdnpo 6 rw 1: the dnpo pin level is set to floating by software. 0: the dnpo pin level is set to 0 by software. xmute 7rw 1: the xmute pin is set to floating by software. 0: the xmute pin is set to 0 by software. the spo flag is special designed to control the po . when the flag spo is set to 1, the po pin is controlled by the combi - nation of the hks pin, hfi pin and hdi pin. the po pin will always be 0 if the flag spo=0. the relation between the dialer i/o function (spo=1) dialer function dialer i/o pin (flag) status result hks hfo hdo po dnpo telephone line on-hook 1 0 0 0 floating break on-hook & hand-free 1 1 0 1 floating make on-hook & hold-line 1 0 1 1 floating make off-hook 0 0 0 1 floating make off-hook & hand-free 0 1 0 1 floating make off-hook & hold-line 0 0 1 1 floating make the following describes the dialer i/o function status machine figure: a 9 ! ! a 9 a 9 5 < 5 < 5 5 < 5 ! ! a 9 a 9 5 5 < ! ! a 9 5 ! ! a 9 5 a ! a 9 5 a ! ! ! a 9 5 8 a 8 a 9 5 8 a 8 a 9 ! ! a 9 5 off-hook: a falling edge to hks pin on-hook: a rising edge to hks pin hfi: a high pulse to hfi pin (hand-free request is generated.) hdi: a low pulse to hdi pin (hold-line request is generated.)
HT95C200/20p/300/30p rev. 0.10 29 october 1, 2002 preliminary line control function register label bits r/w function line (22h) 6~0 ro unused bit, read as 0 linec 7 rw 1: enable the line control function 0: disable the line control function the line control function is enabled by the flag linec conditions source to enable line control function linec operation mode 1 normal or green mode rtc time out interrupt 1 sleep mode port a wake-up rtc time out interrupt 1 idle mode port a wake-up when the line control source is activated, the po pin will be set to high signal. clearing linec to 0 will terminate the line control function and drive po pin outputs low signal. rtc function register label bits r/w function rtcc (24h) 6, 4~0 ro unused bit, read as 0 rtcen 5 rw 1: enable rtc function 0: disable rtc function rtcto 7 rw 1: rtc time-out occurs 0: rtc time-out not occurs "
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; " ; c 8 ( c 8 " g the real time clock (rtc) is used to supply a regular in - ternal interrupt. its time-out period is 1000ms. if the rtc time-out occurs, the interrupt request flag rtcf and the rtcto flag will be set to 1. the interrupt vector for the rtc is 14h. when the interrupt subroutine is serviced, the interrupt request flag (rtcf) will be cleared to 0, but the flag rtcto remain in its original value. if the rtcto flag is not cleared, next rtc time-out interrupt will occur. low battery detection the phone controller provides a circuit that detects the lbin pin voltage level. to enable this detection func - tion, the lben should be written as 1. once this function is enabled, the detection circuit needs 50 s to be stable. after that, the user could read the result from lbfg. the low battery detect function will consume power. for power saving, write 0 to lben if the low battery detec - tion function is unnecessary. > ; : : < ? % > " ! " > 8
: ; 0 the battery low threshold is determined by external r1 and r2 resistors. 1.15= vr2 r1 r2 det v det = 1.15 (r1 r2) r2 if we want to detect v det =2.4v then 2.4v= 1.15 (r1 r2) r2 r1=1.087r2
HT95C200/20p/300/30p rev. 0.10 30 october 1, 2002 preliminary register label bits r/w function lcdc (2dh) frame 0 rw lcd frame selection 0: lcd frame is 64hz 1: lcd frame is 128hz vbias 1 rw lcd bias selection 0: select 1/16 duty and 1/5 bias, com0~com15 are available 1: select 1/8 duty and 1/4 bias, only com8~com15 are available when the 8 com is selected ht95c300/30p: com0~com7 will be optioned to unused pins HT95C200/20p: com0~com7 are disabled, pd0~pd7 are available lben 2 rw low battery detection switch 0: disable the low battery detection 1: enable the low battery detection 3ro unused bit, read as 0 lbfg 4 ro low battery detection flag 1: lbin pin voltage is less than 1.25v 0: lbin pin voltage is not less than 1.25v vcon0 vcon1 5 6 rw lcd contrast adjusting bit6,5=00: lcd voltage supply is 0.66 vlcd bit6,5=10: lcd voltage supply is 0.82 vlcd bit6,5=01: lcd voltage supply is 0.93 vlcd bit6,5=11: lcd voltage supply is 1.00 vlcd lcdon 7 rw 1: turn on the lcd display 0: turn off the lcd display lcdio (28h) 0~4 ro unused bit, read as 0 spe0 5 rw for ht95c300/30p only 0: seg44~seg47 pins are lcd segment output 1: seg44~seg47 pins are pe0~pe3 pins spd0 6 rw for ht95c300/30p only 0: seg36~seg39 pins are lcd segment output 1: seg36~seg39 pins are pd0~pd3 pins spd1 7 rw for ht95c300/30p only 0: seg40~seg43 pins are lcd segment output 1: seg40~seg43 pins are pd4~pd7 pins lcd driver the lcd driver can directly drive an lcd panel with 1/8 duty and 1/4 bias or with 1/16 duty and 1/5 bias, this function is selected by the flag vbias. the frame of this lcd driver may select a 64hz or 128hz by flag frame. lcd driver uses the voltage of the vlcd pin as the power source. to adjust the view angle, the programmer can select the real lcd power by the flags vcon0 and vcon1. the flag lcdon is used to turn on/off the lcd display. note that the vlcd voltage must equal or be less than vdd and vdd2. segment/common to i/o selection for the flexible purpose, some of the lcd common and segment pins are shared with the input/output port. ht95c300/30p provides 12 pins to be selected to segment output pins or i/o pins. HT95C200/20p pro - vides 8 pins to be selected for common output pins or i/o pins. both of the ht95c300/30p and HT95C200/20p provide the lcd common output pins for 8 common or 16 common. the description of the relation between seg - ment pins, common pins and i/o pins are shown on the next page.
HT95C200/20p/300/30p rev. 0.10 31 october 1, 2002 preliminary lcd display memory the phone controller provides an area on embedded data memory for lcd display. the lcd display memory are lo - cated at bank 1bh and can be read and written to, only by indirect addressing mode using mp1. when data is written into the display data area it is automatically read by the lcd driver which then generates the corresponding lcd driv - ing signals, to turn the display on or off, a 1 or 0 is written to the corresponding bit of the display memory, respec - tively. all of the lcd display memories are with random values after the power on reset and unchanged after other reset conditions. com7 to com0 for HT95C200/20p address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40h seg0 com7 com6 com5 com4 com3 com2 com1 com0 41h seg1 com7 com6 com5 com4 com3 com2 com1 com0 com7 com6 com5 com4 com3 com2 com1 com0 56h seg22 com7 com6 com5 com4 com3 com2 com1 com0 57h seg23 com7 com6 com5 com4 com3 com2 com1 com0 com15 to com8 for HT95C200/20p address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 70h seg0 com15 com14 com13 com12 com11 com10 com9 com8 71h seg1 com15 com14 com13 com12 com11 com10 com9 com8 com15 com14 com13 com12 com11 com10 com9 com8 86h seg22 com15 com14 com13 com12 com11 com10 com9 com8 87h seg23 com15 com14 com13 com12 com11 com10 com9 com8 note: when vbias bit set to 1 for 8 com operation (24 8), the lcd ram only map to (70h~87h). com7 to com0 for ht95c300/30p address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 40h seg0 com7 com6 com5 com4 com3 com2 com1 com0 41h seg1 com7 com6 com5 com4 com3 com2 com1 com0 com7 com6 com5 com4 com3 com2 com1 com0 6eh seg46 com7 com6 com5 com4 com3 com2 com1 com0 6fh seg47 com7 com6 com5 com4 com3 com2 com1 com0 com15 to com8 for ht95c300/30p address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 70h seg0 com15 com14 com13 com12 com11 com10 com9 com8 71h seg1 com15 com14 com13 com12 com11 com10 com9 com8 com15 com14 com13 com12 com11 com10 com9 com8 9eh seg46 com15 com14 com13 com12 com11 com10 com9 com8 9fh seg47 com15 com14 com13 com12 com11 com10 com9 com8 note: when vbias bit is set to 1 for 8 com operation (48 8), the lcd ram only map to (70h~9fh).
HT95C200/20p/300/30p rev. 0.10 32 october 1, 2002 preliminary pfd generator register label bits r/w function pfdc (2eh) 3~0 ro unused bit, read as 0 pfden 4 rw 1: enable pfd output 0: disable pfd output, the music pin output low level. pres0 pres1 5 6 rw bit6, 5=00: prescaler output= pfd frequency source/1 bit6, 5=01: prescaler output= pfd frequency source/2 bit6, 5=10: prescaler output= pfd frequency source/4 bit6, 5=11: prescaler output= pfd frequency source/8 fpfd 7 rw 1: the pfd frequency source is 3.58mhz/4 0: the pfd frequency source is 32768hz pfdd (2fh) 7~0 rw pfd data register the pfd (programmable frequency divider) is implemented in the phone controller. it is composed of two portions: a prescaler and a general counter. the prescaler is controlled by the register bits, pres0 and pres1. the general counter is programmed by an 8-bit register pfdd. the source for this generator can be selected from 3.58mhz/4 or 32768hz. to enable the pfd output, write 1 to the pfden bit. the pfdd is inhibited to write while the pfd is disabled. to modify the pfdd contents, the pfd must be enabled. when the generator is disabled, the pfdd is cleared by hardware. pfd output frequency= prescaler output 2(n 1) , where n=the value of the pfdd mask option table the following shows many kinds of mask options in the telephone controller. all these options should be defined in or- der to ensure proper system functions. name mask option wdt wdt source selection rc select the wdt osc to be the wdt source. t1 select the instruction clock to be the wdt source. 32khz select the external 32768hz to be the wdt source. disable disable wdt function. wdtinstr this option defines how to clear the wdt by instruction. one clear instruction the clr wdt can clear the wdt. two clear instructions only when both of the clr wdt1 and clr wdt2 have been executed, then wdt can be cleared. wake-up pa port a wake-up selection. define the activity of wake-up function. all port a have the capability to wake-up the chip from a halt. this wake-up function is selected per bit. pull-high port a pull-high port b pull-high port d pull-high port e pull-high option. this option determines whether the pull-high resistance is viable or not. port a pull-high option is selected per bit. port b pull-high option is selected per bit. port d pull-high option is selected per nibble for ht95c300/30p. port d pull-high option is selected per byte for HT95C200/20p. port e pull-high option is selected per nibble. 8 8

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instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none HT95C200/20p/300/30p rev. 0.10 34 october 1, 2002 preliminary
mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pd to (4) ,pd (4) to (4) ,pd (4) none none to,pd note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pd are cleared. otherwise the to and pd flags remain unchanged. HT95C200/20p/300/30p rev. 0.10 35 october 1, 2002 preliminary
instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) tc2 tc1 to pd ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 36 october 1, 2002 preliminary
and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) tc2 tc1 to pd ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack pc+1 pc addr affected flag(s) tc2 tc1 to pd ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 37 october 1, 2002 preliminary
clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pd) and time-out bit (to) are cleared. operation wdt 00h pd and to 0 affected flag(s) tc2 tc1 to pd ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pd and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pd flags remain unchanged. operation wdt 00h* pd and to 0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pd and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the to and pd flags remain unchanged. operation wdt 00h* pd and to 0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 38 october 1, 2002 preliminary
cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) tc2 tc1 to pd ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) tc2 tc1 to pd ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) tc2 tc1 to pd ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 39 october 1, 2002 preliminary
halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pd) is set and the wdt time-out bit (to) is cleared. operation pc pc+1 pd 1 to 0 affected flag(s) tc2 tc1 to pd ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation pc addr affected flag(s) tc2 tc1 to pd ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 40 october 1, 2002 preliminary
mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) tc2 tc1 to pd ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) tc2 tc1 to pd ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation pc pc+1 affected flag(s) tc2 tc1 to pd ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) tc2 tc1 to pd ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 41 october 1, 2002 preliminary
ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation pc stack affected flag(s) tc2 tc1 to pd ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation pc stack acc x affected flag(s) tc2 tc1 to pd ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation pc stack emi 1 affected flag(s) tc2 tc1 to pd ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 42 october 1, 2002 preliminary
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) tc2 tc1 to pd ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) tc2 tc1 to pd ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 43 october 1, 2002 preliminary
rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) tc2 tc1 to pd ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 44 october 1, 2002 preliminary
set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) tc2 tc1 to pd ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) tc2 tc1 to pd ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 45 october 1, 2002 preliminary
sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) tc2 tc1 to pd ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) tc2 tc1 to pd ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 46 october 1, 2002 preliminary
sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) tc2 tc1 to pd ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 47 october 1, 2002 preliminary
xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) tc2 tc1 to pd ov z ac c HT95C200/20p/300/30p rev. 0.10 48 october 1, 2002 preliminary
package information 128-pin qfp (14 20) outline dimensions symbol dimensions in mm min. nom. max. a 18.80 19.20 b 13.90 14.10 c 24.80 25.20 d 19.90 20.10 e 0.50 f 0.20 g 2.50 3.10 h 3.40 i 0.10 j 0.65 0.95 k 0.10 0.20 0 7 HT95C200/20p/300/30p rev. 0.10 49 october 1, 2002 preliminary ' & 0 + & + & $ : ' 0 . % ; < 5 i 1 . *
HT95C200/20p/300/30p rev. 0.10 50 october 1, 2002 preliminary copyright 2002 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science-based industrial park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (sales office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (shanghai) inc. 7th floor, building 2, no.889, yi shan rd., shanghai, china tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holmate semiconductor, inc. 48531 warm springs boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com

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